----------P0000001F--------------------------
PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237)
SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0000  R-  DMA channel 0	current address		byte  0, then byte 1
0000  -W  DMA channel 0	base address		byte  0, then byte 1
0001  RW  DMA channel 0 word count		byte 0, then byte 1
0002  R-  DMA channel 1	current address		byte  0, then byte 1
0002  -W  DMA channel 1	base address		byte  0, then byte 1
0003  RW  DMA channel 1 word count		byte 0, then byte 1
0004  R-  DMA channel 2	current address		byte  0, then byte 1
0004  -W  DMA channel 2	base address		byte  0, then byte 1
0005  RW  DMA channel 2 word count		byte 0, then byte 1
0006  R-  DMA channel 3	current address		byte  0, then byte 1
0006  -W  DMA channel 3	base address		byte  0, then byte 1
0007  RW  DMA channel 3 word count		byte 0, then byte 1

0008  R-  DMA channel 0-3 status register (see #P0001)
0008  -W  DMA channel 0-3 command register (see #P0002)
0009  -W  DMA channel 0-3 write request register (see #P0003)
000A  RW  DMA channel 0-3 mask register (see #P0004)
000B  -W  DMA channel 0-3 mode register (see #P0005)

000C  -W  DMA channel 0-3 clear byte pointer flip-flop register
	  any write clears LSB/MSB flip-flop of address and counter registers
000D  R-  DMA channel 0-3 temporary register
000D  -W  DMA channel 0-3 master clear register
	  any write causes reset of 8237
000E  -W  DMA channel 0-3 clear mask register
	  any write clears masks for all channels
000F  rW  DMA channel 0-3 write mask register (see #P0006)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 2 is used by the floppy disk controller
	on the IBM PC/XT channel 0 was used for the memory refresh and
	  channel 3 was used by the hard disk controller
	on AT and later machines with two DMA controllers, channel 4 is used
	  as a cascade for channels 0-3
	command and request registers do not exist on a PS/2 DMA controller

Bitfields for DMA channel 0-3 status register:
Bit(s)	Description	(Table P0001)
 7	channel 3 request active
 6	channel 2 request active
 5	channel 1 request active
 4	channel 0 request active
 3	channel terminal count on channel 3
 2	channel terminal count on channel 2
 1	channel terminal count on channel 1
 0	channel terminal count on channel 0
SeeAlso: #P0002,#P0481

Bitfields for DMA channel 0-3 command register:
Bit(s)	Description	(Table P0002)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1 extended write selection
	=0 late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing (two clocks instead of four per transfer)
	=1 normal timing (default)
	=0 compressed timing
 2	=1 enable controller
	=0 enable memory-to-memory
 1-0	channel number
SeeAlso: #P0001,#P0004,#P0005,#P0482

Bitfields for DMA channel 0-3 request register:
Bit(s)	Description	(Table P0003)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0004

Bitfields for DMA channel 0-3 mask register:
Bit(s)	Description	(Table P0004)
 7-3	reserved (0)
 2	=0 clear mask bit
	=1 set mask bit
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0001,#P0002,#P0003,#P0484

Bitfields for DMA channel 0-3 mode register:
Bit(s)	Description	(Table P0005)
 7-6	transfer mode
	00 demand mode
	01 single mode
	10 block mode
	11 cascade mode
 5	direction
	=0 increment address after each transfer
	=1 decrement address
 3-2	operation
	00 verify operation
	01 write to memory
	10 read from memory
	11 reserved
 1-0	channel number
	00 channel 0 select
	01 channel 1 select
	10 channel 2 select
	11 channel 3 select
SeeAlso: #P0002,#P0485

Bitfields for DMA channel 0-3 write mask register:
Bit(s)	Description	(Table P0006)
 7-4	reserved
 3	channel 3 mask bit
 2	channel 2 mask bit
 1	channel 1 mask bit
 0	channel 0 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0004,#P0486
----------P0010001F--------------------------
PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80
SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh

0018  -W  extended function register (see #P0007)
001A  -W  extended function execute register

Bitfields for DMA extended function register:
Bit(s)	Description	(Table P0007)
 7-4	function code (see #P0008)
 3	reserved (0)
 2-0	channel number
	000 channel 0 select
	001 channel 1 select
	010 channel 2 select
	011 channel 3 select
	100 channel 4 select
	101 channel 5 select
	110 channel 6 select
	111 channel 7 select

(Table P0008)
Values for DMA extended function codes (data go to/from PORT 001Ah):
Value	Description		  Parameters  Results
 00h	current address register      -	      CA0,CA1
 02h	write address		      -	      A0,A1,P
 03h	read  address		   A0,A1,P	 -
 04h	write word count register   C0,C1	 -
 05h	read  word count register     -	       C0,C1
 06h	read status register	      -		 S
 07h	mode register		      -		 M
 09h	mask channel		      -		 -
 0Ah	unmask channel		      -		 -
 0Dh	master clear		      -		 -
Note:	CA0/CA1	  LSB/MSB of the current address register
	A0/A1	  LSB/MSB of the base address register
	P	  DMA page address
	C0/C1	  LSB/MSB of the word count register
	S	  status register value (see #P0001, #P0481)
	M	  mode register value (see #P0005, #P0485)
	first, the extended function register is written, then the extended
	  function register execute register is read/written if the function
	  being executing requires

Bitfields for DMA extended mode register:
Bit(s)	Description	(Table P0009)
 7	reserved (0)
 6	=0 8-bit transfer
	=1 16-bit transfer
 5-4	reserved (0)
 3	transfer type
	=0 read from memory
	=1 write to memory
 2	=0 disable memory write
	=1 enable  memory write
 1	reserved (0)
 0	address select
	=0 use 0 as base address
	=1 use a value from base address register
Note:	the IBM PS/2 model 80 technical reference doesn't seem to mention this
	  register's address

----------P0080008F--------------------------
PORT 0080-008F - DMA PAGE REGISTERS (74612)

0080  RW  extra page register (temporary storage)
0081  RW  DMA channel 2 address byte 2
0082  RW  DMA channel 3 address byte 2
0083  RW  DMA channel 1 address byte 2
0084  RW  extra page register
0085  RW  extra page register
0086  RW  extra page register
0087  RW  DMA channel 0 address byte 2
0088  RW  extra page register
0089  RW  DMA channel 6 address byte 2
008A  RW  DMA channel 7 address byte 2
008B  RW  DMA channel 5 address byte 2
008C  RW  extra page register
008D  RW  extra page register
008E  RW  extra page register
008F  RW  DMA refresh page register

----------P00C000DF--------------------------
PORT 00C0-00DF - DMA 2 - SECOND DIRECT MEMORY ACCESS CONTROLLER (8237)

00C0  RW  DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2  RW  DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4  RW  DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6  RW  DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8  RW  DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA  RW  DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC  RW  DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE  RW  DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0  R-  DMA channel 4-7 status register (ISA, EISA) (see #P0481)
00D0  -W  DMA channel 4-7 command register (ISA, EISA) (see #P0482)
00D2  -W  DMA channel 4-7 write request register (ISA, EISA)
00D4  -W  DMA channel 4-7 write single mask register (ISA, EISA) (see #P0484)
00D6  -W  DMA channel 4-7 mode register (ISA, EISA) (see #P0485)
00D8  -W  DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)

00DA  R-  DMA channel 4-7 read temporary register (ISA, EISA)
00DA  -W  DMA channel 4-7 master clear (ISA, EISA)
00DC  -W  DMA channel 4-7 clear mask register (ISA, EISA)
00DE  -W  DMA channel 4-7 write mask register (ISA, EISA) (see #P0486)
Notes:	the temporary register is used as holding register in memory-to-memory
	  DMA transfers; it holds the last transferred byte
	channel 4 is used for cascading the first (8-bit) DMA controller
	base/current address registers can only address the memory in 16-bit
	  words (i.e. they contain lines A1-A16 of the address bus with line
	  A0 always equal to 0); base/current word count registers contain the
	  number of 16-bit words
	command and request registers do not exist on PS/2 DMA controller

Bitfields for DMA channel 4-7 status register:
Bit(s)	Description	(Table P0481)
 7 = 1	channel 7 request
 6 = 1	channel 6 request
 5 = 1	channel 5 request
 4 = 1	channel 4 request
 3 = 1	terminal count on channel 7
 2 = 1	terminal count on channel 6
 1 = 1	terminal count on channel 5
 0 = 1	terminal count on channel 4
SeeAlso: #P0001,#P0482

Bitfields for DMA channel 4-7 command register:
Bit(s)	Description	(Table P0482)
 7	DACK sense active high
 6	DREQ sense active high
 5	=1  extended write selection
	=0  late write selection
 4	rotating priority instead of fixed priority
 3	compressed timing
 2	=1  enable controller
	=0  enable memory-to-memory transfer
 1-0	channel number (00 = 4 to 11 = 7)
SeeAlso: #P0002,#P0481,#P0484

Bitfields for DMA channel 4-7 request register:
Bit(s)	Description	(Table P0483)
 7-3	reserved (0)
 2	=0 clear request bit
	=1 set request bit
 1-0	channel number
	00 channel 4 select
	01 channel 5 select
	10 channel 6 select
	11 channel 7 select
SeeAlso: #P0003,#P0484

Bitfields for DMA channel 4-7 write single mask register:
Bit(s)	Description	(Table P0484)
 7-3	reserved
 2	=0  clear mask bit
	=1  set mask bit
 1-0	channel select
	00 channel 4 select
	01 channel 5 select
	10 channel 6 select
	11 channel 7 select
SeeAlso: #P0004,#P0482

Bitfields for DMA channel 4-7 mode register:
Bit(s)	Description	(Table P0485)
 7-6	transfer mode
	00  demand mode
	01  single mode
	10  block mode
	11  cascade mode
 5	direction
	0  address increment select
	1  address decrement select
 4	autoinitialisation enabled
 3-2	operation
	00  verify operation
	01  write to memory
	10  read from memory
	11  reserved
 1-0	channel number
	00  channel 4 select
	01  channel 5 select
	10  channel 6 select
	11  channel 7 select
SeeAlso: #P0005,#P0484

Bitfields for DMA channel 4-7 write mask register:
Bit(s)	Description	(Table P0486)
 7-4	reserved
 3	channel 7 mask bit
 2	channel 6 mask bit
 1	channel 5 mask bit
 0	channel 4 mask bit
Note:	each mask bit is automatically set when the corresponding channel
	  reaches terminal count or an extenal EOP sigmal is received
SeeAlso: #P0484,#P0006

